Design and implementation of high speed QSPI memory controller

This paper describes a new high speed Quad Serial Peripheral Interface (QSPI) NOR flash memory controller, which can work in a mixed single-data-rate/double-data-rate (SDR/DDR) mode. The proposed controller can support code eXecute In Place (XIP) operation as well as classic demand paging. The operation frequency ranges from larger than 0 up to 133 MHz for SDR write and read operations, or from larger than 0 up to 80 MHz for DDR read operation. The controller features an efficient calibration method for maximizing margin for receiving data. This QSPI memory controller prototype is designed and implemented on Xilinx Zynq-7020 Field-programmable gate array (FPGA).