A Low Power Area Efficient Full Custom 3-Read 3-Write General Purpose Register in 65nm Technology

The design of a full custom 32×32 bit general purpose register (GPR) file with three read ports and three write ports for a microprocessor in SMIC 65 nm Logic Low-Leakage CMOS technology was presented. During the design process, a full custom method with specific circuit construction including robust cell array and optimized decoder circuit was proposed in order to control power consumption and design area. For test mode only, an internal circuitry was built to resolve multiple write-port address collisions. With respect to conventional semi-custom solution, the full custom approach achieves 28% saving of power as well as 43% of area. Its operating frequency can reach up to 900 MHz, the occupied area is 0.0311 mm² and the average power dissipation comes to 5.83 mW at 1.2 V supply voltage which is also superior to some previous designs.