Hardware Architecture Design of Image Preprocessing and Phase Calculating Algorithms Based on FPGA

In order to implement real-time image preprocessing and fast phase calculating problem, this paper presents a hardware circuit structure by making use of FPGA (Field Programmable Gate Array). This hardware circuit structure can solve the real-time fast problem of image preprocessing and phase calculating. By using look ahead multiplier, median filter, IP Core, etc. we build a hardware circuit algorithm model which is able to reflect FPGA´s high-speed, parallel computing capabilities in the processing some algorithms. Applying the structure to the front part of the three-dimensional measuring system does not require additional processing time. Imaging experiments showed that: using the hardware architecture for image preprocessing and phase calculating after obtaining sensor images, non-uniformity correction (based on calibration), blind-pixel compensation (median filter) can be done in real-time, and the data of transmission can reduced because of transferring results of phase calculating. Design of this hardware architecture is a high efficient, fast front processing solution, and it has been verified in the three-dimensional system.