Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

Author

Hung-Chih Tsai ; Yadav, Yogendra ; Ruey-Hsin Liou ; Kuo-Ming Wu ; Yi-Chin Lin ; Chenhsin Lien

Author_Institution

Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

Volume

62

Issue

6

fYear

2015

fDate

Jun-15

Firstpage

1958

Lastpage

1963

Abstract

A CMOS compatible high-voltage shallow trench isolation (STI) drain extended MOS (DEMOS) transistor is fabricated and its electrical characteristics are studied. A local p-well (PW) plate served as a reduced surface field is adopted to enhance the breakdown voltage (BV) by reducing the effective doping concentration of the accumulation region. The conformal-mapping method is used to evaluate the BV of this 2-D STI DEMOS structure theoretically. A BV model, which relates the BV to the width of the accumulation region x_a and the overlap/underlap O_p between the local PW plate and the STI, is derived. The predictions of this model agree very well with both the experimental data and the technology computer-aided-design simulations.

Keywords

CMOS integrated circuits; MOSFET; doping profiles; isolation technology; semiconductor device breakdown; semiconductor device models; CMOS compatible RESURF STI drain; DEMOS transistor; breakdown voltage model; computer-aided-design simulations; conformal-mapping method; doping concentration; drain extended MOS transistor; electrical characteristics; high-voltage shallow trench isolation; local p-well plate; reduced surface field; Conformal mapping; Doping; Electric breakdown; JFETs; Niobium; Semiconductor process modeling; Drain extended MOS (DEMOS); lateral double-diffused MOS (LDMOS); reduced surface field (RESURF);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2015.2418291

Filename

7109961