Title :
New topology with reduced number of switches in asymmetrical cascaded multilevel inverter
Author :
Gautam, Shivam Prakash ; Gupta, Swastik ; Pattnaik, Swapnajit ; Singh, V.
Author_Institution :
Dept. of Electr. Eng., Nat. Inst. of Technol. Raipur, Raipur, India
Abstract :
Use of multilevel inverters has been increased rapidly in the recent years, due to its tremendous popularity in reduced voltage stress across power switches and low total harmonic distortion in output waveform. Various topology of multilevel inverter has been proposed. In this paper a new nine level single phase multilevel inverter topology has been presented and comparison is made between proposed topology and conventional topology and then the generalize form is presented. Multi-carrier pulse width modulation technique has been adopted for switching purpose. The output voltage THD for 9-level inverter is 6.2% and for 27-level inverter is 2.68%, whereas the output current THD for 9-level inverter is 2.01% and for 27-level inverter is 0.92%. The simulation results are based on MATLAB/SIMULINK software.
Keywords :
PWM invertors; harmonic distortion; switching convertors; 27-level inverter; asymmetrical cascaded multilevel inverter; multicarrier pulse width modulation technique; nine level single phase multilevel inverter topology; output voltage THD; MATLAB/SIMULINK; Multilevel inverter; THD; multi-carrier pulse width modulation;
Conference_Titel :
Communication and Computing (ARTCom 2013), Fifth International Conference on Advances in Recent Technologies in
Conference_Location :
Bangalore
Print_ISBN :
978-1-84919-842-4
DOI :
10.1049/cp.2013.2230