A Delay Slot Scheduling Framework for VLIW Architectures in Assembly-Level

A delay slot scheduling framework for VLIW architectures is presented in this paper. In this framework, an assembly data dependence graph is proposed to describe the data dependences among instructions in a basic block. An assembly control flow graph is also proposed to describe control relations among basic blocks. With the help of predicate analysis technology, majority invalid control flows are detected. Along the edges in these two graphs, instructions are selected to be filled into delay slots. Additionally, a scheme to balance the local scheduling and the global scheduling is proposed in this paper. This framework is evaluated by several experiments on the SuperV-DSP processor. And the results demonstrate the effectiveness of the new approach.