Novel Differential Flip-Flops Using Neuron-MOS Transistors

Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch double edge-triggered(IL-DET) flip-flop. In the new differential flip-flops, a pair of n-channel neuron-MOS transistors is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified by employing the neuron-MOS transistors. In the proposed configurations, the edge-triggering operations are achieved by a narrow pulse produced by two input gates of multiple-input neuron-MOS transistors receiving a clock and a delayed clock, respectively. In comparison with neuron-MOS-based differential master-slave flip-flop, the IL-SET configuration has reduced transistor count and lower power consumption. The HSPICE simulation using TSMC 0.35μm 2-ploy 4-metal CMOS technology validated the effectiveness of the proposed approach.