DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing

In this paper, we propose a novel hybrid Dense-Sparse Network-on-Chip (DSNOC) design that takes advantage of both dense and sparse networks. The NoC paradigm is introduced to solve the communication bottleneck and improve system scalability for multicore processors with hundreds or even thousands of cores. Dense mesh network has been used widely in NoCs due to the simplicity of the design and implementation. However the scalability of dense network can be a bottleneck in systems with high traffic volume. Sparse network has been proposed to provide higher bandwidth and better scalability than the dense network, while the size of the interconnection system becomes impractical for large systems. By combining the benefits of both networks, system performance and efficiency can be improved with a proper hybrid design. We analyse and investigate router utilization and traffic distribution of typical mesh networks. The hybrid solution is explored with theoretical analysis and implementation considerations. Experiments are performed by using a full system simulation environment. The evaluation results show that, compared with the dense network, the average network latency and energy delay product of DSNOC are improved by 10.3% and 33% respectively.