DocumentCode
692163
Title
Recent progress and future directions in NAND Flash scaling
Author
Goda, Akira
Author_Institution
Micron Technol., Boise, ID, USA
fYear
2013
fDate
12-14 Aug. 2013
Firstpage
1
Lastpage
4
Abstract
This paper discusses challenges and opportunities of NAND cell scaling. The conventional wrap floating gate (FG) cell has many scaling challenges including high aspect ratio, cell-to-cell interference and increase in E-field. Various planar cell technologies have been suggested. Among them, a planar FG cell has demonstrated the best performance and reliability at the middle 10 nm node. Key requirements for the 3D NAND as a 10 nm equivalent NAND have been discussed.
Keywords
NAND circuits; circuit reliability; logic gates; NAND flash scaling; cell-to-cell interference; floating gate cell; high aspect ratio; planar FG cell; reliability; size 10 nm; Computer architecture; Interference; Logic gates; Microprocessors; Reliability; Three-dimensional displays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Non-Volatile Memory Technology Symposium (NVMTS), 2013 13th
Conference_Location
Minneapolis, MN
Type
conf
DOI
10.1109/NVMTS.2013.6851055
Filename
6851055
Link To Document