Power-aware inductor analysis in resonant clock networks

The clock distribution network in a synchronous digital circuit delivers the clock signal to every storage element (i.e., clock sink) in the circuit. With the continued increase of clock frequency and clock resources, the clock networks consume substantially large dynamic power. Resonant clock network is one of efficient structures to reduce clock power consumption by storing electric energy to the inserted inductors rather than dissipating through nMOS elements of clock buffers. In the resonant clock network, LC tank placement and sizing are two of the most important problems to minimize power consumption and area overhead. We analyze power consumption of 3-level H-tree by varying the operation frequencies, LC tank placements, and sizes. Through the analyses, we show that the calculation of LC resonant frequency based on the conventional formulation causes a less power reduction than what we normally expect, especially the accuracy of the calculation becomes worse as the clock frequency (> 5GHz) increases.