Scan chain swapping using TSVs for test power reduction in 3D-IC

Author

Ingeol Lee ; Jaeseok Park ; Sungho Kang

Author_Institution

Yonsei Univ., Seoul, South Korea

fYear

2013

fDate

17-19 Nov. 2013

Firstpage

170

Lastpage

171

Abstract

Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.

Keywords

design for testability; integrated circuit design; integrated circuit reliability; integrated circuit testing; power consumption; three-dimensional integrated circuits; 3D-IC; TSV; X-filling; chip design; design for testability; heat problems; power consumption; scan chain swapping method; scan structure; shift power; swapping algorithm; system reliability; test mode; test power reduction; Algorithm design and analysis; Filling; Flip-flops; Heat sinks; Integrated circuits; Power demand; Three-dimensional displays; power reduction; scan chain swapping; through silicon via;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2013 International

Conference_Location

Busan

Type

conf

DOI

10.1109/ISOCC.2013.6863963

Filename

6863963