Pulsed-Vdd: Synchronous circuit design without clock network

Almost all digital circuits designed these days are synchronous ones. A clock is responsible for synchronization and is distributed via clock (distribution) network, which requires significant design time and effort and incurs extra area and wirelength. We advocate that synchronous circuit can be designed without clock network. Instead, power supply V_dd network is made to carry periodic negative pulses. A new sequencing element is proposed, which internally generates a positive pulse with each negative pulse on V_dd and then latches input data using that pulse. Since pulses are delivered over the V_dd network, which inherently has small RC value, skew becomes smaller, which is another advantage.