DocumentCode
692524
Title
Test scheduling using Ant Colony Optimization for 3D integrated circuits
Author
Inhyuk Choi ; Taewoo Han ; Sungho Kang
Author_Institution
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear
2013
fDate
17-19 Nov. 2013
Abstract
Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.
Keywords
ant colony optimisation; integrated circuit testing; three-dimensional integrated circuits; 2D IC; 3D integrated circuits; ACO; IC test scheduling; TAM; TSV; constraint factors; test access mechanism; test pin count constraint; thermal constraint; through silicon via; Computer architecture; Processor scheduling; Scheduling; System-on-chip; Three-dimensional displays; ant colony optimization; test scheduling; three-dimensional integrated circuit; through silicon via;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2013 International
Conference_Location
Busan
Type
conf
DOI
10.1109/ISOCC.2013.6863973
Filename
6863973
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