The effects of integrated controller techniques on the flash memories

Author

Abadies, Hearty Z. ; Alvarez, Anastacia B. ; Madamba, Joy Alinda R. ; Alarcon, Louis P.

Author_Institution

Microelectron. & Microprocessors Lab., Univ. of the Philippines Diliman, Quezon City, Philippines

fYear

2013

fDate

17-19 Nov. 2013

Abstract

This paper describes flash controller techniques: (1) split cache memory management which addresses architectural level issues of flash memories; (2) wear levelling and garbage collection which spreads wear-out; (3) density alteration which mitigates the effects of flash cell aging; and (4) Reed-Solomon error correction. All techniques, except RS code, are modelled and simulated in Matlab. The RS code is implemented in 65nm CMOS technology. The proposed controller increased the flash memory lifetime by 128X with a 4.1X increase in latency.

Keywords

CMOS memory circuits; Reed-Solomon codes; cache storage; error correction; flash memories; integrated circuit reliability; CMOS technology; Matlab; RS code; Reed-Solomon error correction; architectural level issue; density alteration; flash cell aging; flash controller technique; flash memory; flash memory lifetime; garbage collection; integrated controller technique; size 65 nm; split cache memory management; wear levelling; wear-out; Algorithm design and analysis; Cache memory; Error correction codes; MATLAB; Mathematical model; Split gate flash memory cells; density control; error correction code; flash memory controller; garbage collection; split cache; wear-levelling;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2013 International

Conference_Location

Busan

Type

conf

DOI

10.1109/ISOCC.2013.6863984

Filename

6863984