High-performance low-power application processor integrated with modem processor

An architecture is proposed to design a single chip with an application processor (AP) and a modem processor (MP). As an aggressive challenge, the MP´s dedicated memory is removed to share the main memory with the AP. In addition, an autonomous power management (APM) is presented to reduce the power consumption of time-constrained tasks such as wireless communication. The APM is designed without the intervention of the microprocessors, to deal with the random and sparse data pattern of voice communication. For the architectural exploration, an electronic system-level simulation is performed for verifying the performance and power consumption. Through the simulation results, the proposed architecture exhibits small size, good performance and energy consumption.