• DocumentCode
    692568
  • Title

    A low power GPS/Galileo/GLONASS receiver in 65nm CMOS

  • Author

    Huijung Kim ; Jeong-Hyun Choi ; Sang-Yun Lee ; Taewan Kim ; Jung-woo Kim ; Jong-Dae Bae ; Chaehag Yi ; Hyunwon Moon

  • Author_Institution
    M&C Dev., Samsung Electron. Co. Ltd., Yongin, South Korea
  • fYear
    2013
  • fDate
    17-19 Nov. 2013
  • Firstpage
    241
  • Lastpage
    244
  • Abstract
    A low power GPS/Galileo/GLONASS receiver is presented. The single chip supports GPS/Galileo and GLONASS operation simultaneously. To operate both application simultaneously, two mixers and two baseband filters are used. The chip size is 3.24 mm2 including bonding PAD. The system noise figure (NF) is 1.95 dB including SAW filter which loss is 1 dB. Power consumption is 23.6 mW for GPS/Galileo operation and 25.4 mW for GLONASS operation from 1.2V supply.
  • Keywords
    CMOS integrated circuits; Global Positioning System; mixers (circuits); radio receivers; GLONASS receiver; Galileo receiver; SAW filter; baseband filters; bonding PAD; loss 1 dB; low power GPS receiver; mixers; noise figure 1.95 dB; power 23.6 mW; power 25.4 mW; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Gain; Global Positioning System; Mixers; Noise measurement; Radio frequency; Receivers; 65nm; CMOS; Channel selection filter; GLONASS; GPS; Galileo; LNA; Mixer; RF receiver;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2013 International
  • Conference_Location
    Busan
  • Type

    conf

  • DOI
    10.1109/ISOCC.2013.6864017
  • Filename
    6864017
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=692568