Novel high electrical quality seven-transistor memory cell with asymmetrical ground gating

A new asymmetrically ground-gated seven-transistor (7T) SRAM cell is proposed in this paper for providing a low leakage high data stability SLEEP mode in memory circuits. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by 2.23x and 54.22% during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a TSMC 65nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a memory array is enhanced by 2.59x with the proposed asymmetrically ground-gated 7T memory cells as compared to the conventional ground-gated 6T SRAM cells.