Fast synchronization algorithm for the Forward Error Correction in IEEE Standard 802.3

A shortened cyclic code (known as Forward Error Correction [FEC]) aimed at increasing link budget and Bit Error Rate (BER) performance is introduced in section 74 of IEEE Standard 802.3. FEC is widely used in High Speed Serdes communication applications like 10G/40G Ethernet. This paper proposes a synchronize algorithm for chip implementation which quickly detect the boundary of the received code block. Compared with the algorithm outlined in the 802.3 standard, the proposed one improves synchronization time by three orders of magnitude.