A low jitter spread spectrum clock generator using varactor delay line

A spread spectrum clock generator (SSCG) is realized using varactor based delay line and a dejittering PLL. This varactor based delay line utilizes the delay-modulation to phase-modulation property to generate an intermediate spread-spectrum input clock. This SSCG has been fabricated in a 0.18μm double-poly six metal CMOS process and it consumes 35mW from the supply of 1.8V. The proposed SSCG can generate clocks 27MHz, 54MHz and 108MHz with centre-spread ratios of +/-0.25%. The measured peak-to-peak cycle-to-cycle jitter is less than 100ps and the measured electromagnetic interference reduction amount is 2.8dB.