Design and evaluation of a novel reconfigurable ALU based on FPGA

Reconfigurable architecture requires many processing elements (PEs) and configuration switches for reconfigurable module. High performance is necessary for the reconfigurable module. In order to achieve data-intensive computation, we design a novel reconfigurable ALU for 32bit high-performance DSP. The ALU consists of sixteen unified arithmetic PEs, four configurable registers and one shared interconnection network, and efficiently achieves different arithmetic operations, such as integer, floating-point number and reconfigurable computation for various applications. Evaluating results show that the proposed reconfigurable ALU can work at 250.43MHz adopting FPGA XC6VSX475T-2FF1156 with lower power consumption and Look-Up Tables (LUTs).