Configuration modes of FPGA chips for embedded systems applied to advanced manufacturing technology

The work presented in this paper focuses on the configuration modes of FPGA (field programmable gate array) chips. The methods adopted extensively by the authors are mainly derived from the data sheets provided by the chip manufacturers and the technical requirements of advanced manufacturing. When the FPGA chips work as the special function modules of the embedded systems, the PS (passive serial) mode and the JTAG (joint test action group) mode are frequently used by the designers, with the advantage described as follows: the connection-circuit is simple and there is no limitation of minimum clock frequency. The configuration circuit and the integral configuration timing for the two modes are given in this paper. As to the FPGA chips of multiple configuration modes, we can select the most efficient mode according to the field need of advanced manufacturing.