Poster abstract: ASFECs - Using approximately synchronized fetch-and-execute cycles as basic operation cycles for Wireless Sensor Networks

I present preliminary results of my work on an architecture for Wireless Sensor Networks (nets) that realizes the novel concept of ASFECs (approximately synchronized fetch-andexecute cycles). This architecture extends the classical fetch-and-execute cycles of computers by syncing phases. It guarantees a consistent value of the instruction pointer for all (sensor) nodes and a maximum skew between the starting times of the corresponding instructions on the nodes. In addition, I present my current work. I show how ASFECs can process net-assemblies. So far, I have studied centralized nets, only. I expect that ASFECs can be a important step towards fully deterministic, hard real time measurements fulfilled by nets.