A hybrid vertical interconnect for three-dimensional network-on-chip

Three-dimensional network-on-chip (3D NoC) applying Through-Silicon-Vias (TSVs) is the most promising process in achieving higher network bandwidth, lower latency and lower power consumption. Unfortunately, the fabrication process of TSV connection has not matured yet, which results in poor vertical links yield thus the yield of 3D NoC decreases sharply with the growth in the number of TSVs. To ensure the yield of the 3D NoC, in this paper we propose a hybrid vertical interconnect scheme which minimizes the number of TSV by sharing vertical links through vertical routers.