• DocumentCode
    695234
  • Title

    Scaling distributed cache hierarchies through computation and data co-scheduling

  • Author

    Beckmann, Nathan ; Po-An Tsai ; Sanchez, Daniel

  • Author_Institution
    Massachusetts Inst. of Technol., Cambridge, MA, USA
  • fYear
    2015
  • fDate
    7-11 Feb. 2015
  • Firstpage
    538
  • Lastpage
    550
  • Abstract
    Cache hierarchies are increasingly non-uniform, so for systems to scale efficiently, data must be close to the threads that use it. Moreover, cache capacity is limited and contended among threads, introducing complex capacity/latency tradeoffs. Prior NUCA schemes have focused on managing data to reduce access latency, but have ignored thread placement; and applying prior NUMA thread placement schemes to NUCA is inefficient, as capacity, not bandwidth, is the main constraint. We present CDCS, a technique to jointly place threads and data in multicores with distributed shared caches. We develop novel monitoring hardware that enables fine-grained space allocation on large caches, and data movement support to allow frequent full-chip reconfigurations. On a 64-core system, CDCS outperforms an S-NUCA LLC by 46% on average (up to 76%) in weighted speedup and saves 36% of system energy. CDCS also outperforms state-of-the-art NUCA schemes under different thread scheduling policies.
  • Keywords
    cache storage; distributed shared memory systems; multi-threading; processor scheduling; CDCS; NUCA scheme; NUMA thread placement scheme; S-NUCA LLC; access latency; cache capacity; complex capacity/latency tradeoff; data coscheduling; data movement support; distributed shared cache; fine-grained space allocation; full-chip reconfiguration; monitoring hardware; scaling distributed cache hierarchy; system energy; thread scheduling policy; weighted speedup; Bandwidth; Hardware; Instruction sets; Monitoring; Resource management; System-on-chip; NUCA; cache; partitioning; thread scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on
  • Conference_Location
    Burlingame, CA
  • Type

    conf

  • DOI
    10.1109/HPCA.2015.7056061
  • Filename
    7056061