Physical verification flow for hierarchical analog ic design constraints

Design constraints describe the intent of IC designers when developing electronic circuits. Constraints from, e.g., electrical and thermal domains are transformed into corresponding physical constraints for layout design. Physical constraints can also be derived from circuit patterns or extracted layout netlists. The constraint verification is of utmost importance to guarantee the intended function of the final IC. Individual constraints often span multiple hierarchy levels, thus requiring a fully hierarchical verification approach. A novel, modular, and extensible industrial-strength approach is presented to (1) derive analog-focused design constraints from an existing circuit or extracted layout netlist, and (2) verify analog constraints such as clustering, matched orientation, matched parameters, alignment, and symmetry across multiple design hierarchy levels. Experimental results for real-world automotive IC designs demonstrate its feasibility.