Tutorial paper: Parallel architectures for model predictive control

This tutorial paper surveys recent developments in parallel computer architecture, focusing on the field-programmable gate array and the graphics processor. We aim to illustrate the potential of these architectures for the type of high-speed numerical computation required in on-line optimization for model predictive control. While significant performance advantages can be gained by migrating existing control algorithms to these processor architectures, in order to realise their full potential, further research is needed at the boundary of control theory, digital electronics, and computer architecture. We survey some of the open questions in this area.