Architectures for arithmetic coding in image compression

In this work we present and evaluate new architectures for the arithmetic encoding and decoding of multilevel images. Arithmetic coding is of great interest due to the excellent results that it gives. On the other hand, the complexity of its implementation has always gone against it and its different applications usually suffer from a high computational cost, slowness or both. By introducing a new memory scheme, based on a cache memory, we solve the classic inconveniences of multilevel arithmetic codification hardware, obtaining architectures that are simpler and faster than the previous ones.