A high speed bit plane coder for JPEG 2000 and it´s FPGA implementation

In this paper an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm targeting its FPGA implementation is proposed. Although several speed up techniques exist, we present architecture whose performance is improved based on detailed analysis of data path used to obtain context windows. Multiplexer based coding style is adapted to utilize the resources optimally. The proposed design works at 67 MHz after post placement and routing on Xilinx XC2V1000 device. Even though 18 bit planes are used, the implementation results show that the consumption of logic resources in terms of LUTs, slices and flip-flop slices have reduced drastically compared to that of reported designs [1, 2, 3, 4, 5 and 6]. Moreover, power consumption is also moderate.