Design of a pipelined R4SDF processor

A pipelined architecture for a 16-point word-serial R4SDF Fast Fourier Transform processor is presented. In this design, a pipelined complex multiplier which consists of pipelined real multipliers is used in order to increase the speed of the processor. The architecture of R4SDF is itself pipelined, but it is further pipelined in this paper and is called a pipelined R4SDF. The evaluation of the b-bit word length design shows that a speed up of (b/3)+1 with respect to a nonpipelined design is achieved. The average Signal to Error Ratio of the designed R4SDF processor for a word length of 9 bits, b=9, is 30.70 dB. The Speed Up for this word length is 4.