A high performance and low power hardware architecture for H.264 CAVLC algorithm

Author

Sahin, Esra ; Hamzaoglu, Ilker

Author_Institution

Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey

fYear

2005

fDate

4-8 Sept. 2005

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a high performance and low power hardware architecture for real-time implementation of Context Adaptive Variable Length Coding (CAVLC) algorithm used in H.264 / MPEG4 Part 10 video coding standard. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 76 MHz in a Xilinx Virtex II FPGA and it is verified to work at 233 MHz in a 0.18μ ASIC implementation. The FPGA and ASIC implementations can code 22 and 67 VGA frames (640×480) per second respectively.

Keywords

adaptive codes; application specific integrated circuits; data compression; field programmable gate arrays; hardware description languages; variable length codes; video coding; ASIC implementation; H.264 CAVLC algorithm; H.264-MPEG4 Part 10 video coding standard; VGA frame; Verilog HDL; Verilog RTL code; Xilinx Virtex II FPGA; context adaptive variable length coding algorithm; frequency 76 MHz; hardware architecture; portable application; size 0.18 mum; Algorithm design and analysis; Encoding; Field programmable gate arrays; Hardware; Hardware design languages; Radiation detectors; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Conference, 2005 13th European

Conference_Location

Antalya

Print_ISBN

978-160-4238-21-1

Type

conf

Filename

7078272