A high performance and low cost hardware architecture for H.264 transform and quantization algorithms

Author

Tasdizen, Ozgur ; Hamzaoglu, Ilker

Author_Institution

Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey

fYear

2005

fDate

4-8 Sept. 2005

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The hardware architecture is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 81 MHz in a Xilinx Virtex II FPGA and it is verified to work at 210 MHz in a 0.18μ ASIC implementation. The FPGA and ASIC implementations can code 27 and 70 VGA frames (640×480) per second respectively.

Keywords

application specific integrated circuits; data compression; field programmable gate arrays; inverse transforms; video coding; ASIC; H.264 transform; H.264/MPEG4 part 10 video coding standard; VGA frame; Verilog HDL; Verilog RTL code; Xilinx Virtex II FPGA; application-specific integrated circuit; field programmable gate array; forward transform; frequency 210 MHz; frequency 81 MHz; inverse transform; low cost hardware architecture; quantization algorithm; reconfigurable datapath; size 0.18 mum; video graphics array; Field programmable gate arrays; Hardware; Hardware design languages; Laplace equations; Quantization (signal); Registers; Transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Conference, 2005 13th European

Conference_Location

Antalya

Print_ISBN

978-160-4238-21-1

Type

conf

Filename

7078360