Design flow improvements for embedded wireless receivers

Complexity of modern communication systems, particularly in the wireless domain, grows at an astounding rate. The algorithmic complexity significantly outpaces the growth in complexity of underlying silicon implementations. Even more dramatically, algorithmic complexity outpaces design productivity. Primarily responsible for the second point is the fragmentation of the design process caused by the extremely heterogeneous nature of modern EDA tools required in wireless communication designs. Such design flows lead to numerous inconsistent design representations, each of them tackling only a specific aspect of the development while neglecting important properties for other design aspects. A permanent rewriting of the design description is required due to the iterative nature of the design process. To overcome such inconsistencies and speed up the process, we present in this paper an automated transition from a high level algorithmic description of a synchronous data flow model to a VSIA compliant Virtual Prototype for an industry-designed UMTS receiver. This automatic translation of algorithmic descriptions is embedded in a consistent design methodology supporting hardware/software co-design as well as efficient testing at all abstraction levels of the design process.