• DocumentCode
    701221
  • Title

    Design and implementation of a digital down converter chip

  • Author

    Sjostrom, Ulf ; Carlsson, Magnus ; Horlin, Magnus

  • Author_Institution
    National Defence Research Establishment, Box 1165, S-581 11 Linköping, Sweden
  • fYear
    1996
  • fDate
    10-13 Sept. 1996
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The design and implementation of a CMOS ASIC containing a digital down converter and a channel equalizer for a digital array antenna system is presented. The chip performs nearly 342×106 MAC/s (multiply-accumulate/second) at an internal bit-rate of 51.6 MHz. The circuit is based on a highly flexible architecture with few full-custom bit-serial arithmetic units.
  • Keywords
    Arrays; Band-pass filters; Clocks; Equalizers; Finite impulse response filters; Power dissipation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Signal Processing Conference, 1996. EUSIPCO 1996. 8th
  • Conference_Location
    Trieste, Italy
  • Print_ISBN
    978-888-6179-83-6
  • Type

    conf

  • Filename
    7082946
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=701221