GlYFF: A framework for global yield and floorplan aware design optimization

Diminishing yields for modern CMOS and emerging technologies have become a major growing concern for IC manufacturers due to its direct impact on revenue. To this end, “Design for Yield (DFY)” have been proposed to proactively address manufacturing yield issues in the system design stage. While many DFY approaches have been developed for caches, GPUs and CPUs, they remain decoupled from each other, which is not ideal for modern microprocessors or MPSoCs that integrate multiple components onto a single die. In this paper we introduce “Global Yield and Floorplan Aware Design Optimization Framework (GlYFF)”, a holistic computer-aided DFY framework that unifies redundancy based yield-centric design optimizations and floorplanning for MP-SoCs. GlYFF recognizes the different yield enhancement strategies for different on-die components, and is able to output detailed floorplans for accurate area/performance measurements. We demonstrate that compared to a segregated DFY methodology, GlYFF can achieve ~20% improvement in yield-per-area, a metric strongly correlated to revenue.