LBIST pattern reduction by learning ATPG test cube properties

Logic built-in self-test (LBIST) is commonly used for testing integrated circuits (ICs) in production and in the field. Due to the random nature of LBIST patterns, activation of random-pattern-resistant faults requires the application of numerous patterns, thus increasing test time in the field. In this work, we introduce a novel method to reduce LBIST pattern count and LBIST test time. The presented technique collects deterministic pattern properties to guide our deterministic test (DT) cell selection and insertion algorithm. The inserted DT cells enhance LBIST patterns quality and reduce pattern count by introducing deterministic-like properties. Experimental results on academic benchmarks and industry designs demonstrate 30% to 70% reduction in pattern count.