Temperature aware refresh for DRAM performance improvement in 3D ICs

Three-dimensional (3D) integration allows IC designs to stack DRAM directly on the top of execution units, which greatly reduces DRAM access latency and optimizes energy consumption. Unfortunately, the heat generated by the processor unit cannot be effectively dissipated. As a result, DRAM operation temperature is undesirably increased. Due to the fact that 3D stacked DRAM operates under a severe thermal condition, conventional designs based on the peak temperature lead to a high refresh rate, which introduces large performance penalty in 3D stacked DRAM. To address this problem, we propose the Temperature Aware Refresh (TAR) technique for 3D stacked DRAM. The goal is to mitigate this performance penalty by adjusting the refresh rates of DRAM banks based on the actual thermal conditions at their locations. As a result, only banks that work in the peak temperature refresh frequently, and the rest of banks can be refreshed at a lower rate. This enables more read and write accesses which improvements the overall system performance.