Application and OS unconscious power manager for SoC systems

The paper¹ describes a dynamic power management (DPM) strategy independent from application and operating system layers, but easily controllable by these layers. Challenges in defining an efficient power management policy include a relevant prediction mechanism of idle period of hardware components and the ability to wake-up components in sleep state such that time penalties induced by the power up operation do not affect application performance. We propose a power management technique based on a history graph built dynamically from the global functional states of the hardware components in the architecture. The history graph reflects the system functional states induced by the application tasks mapped and scheduled on hardware units whatever the operating system considered. The history graph captures correlations between functional states of hardware units and the timing in state evolution. Based on the history graph, power gating or clock gating is set to hardware units depending on the length of their predicted idle period. Wake-up events for power gated hardware units are also scheduled to limit impact of power up penalties. The policy has been analyzed through real practical benchmarks within the Synopsys Platform Architect framework.