6-T SRAM performance assessment with stacked silicon nanowire MOSFETs

This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire (NW) MOSFETs. To achieve high density design while preserving performance, different numbers of stacked NW MOSFETs are investigated via three-dimensional TCAD simulation. Due to tradeoff between read stability and writeability margins, adjusting the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking nanowires technique is used, another design issue with various stacked transistors has to be taken into account. This work simulates butterfly curves and N-curves to assess the device performance and provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. It is suggested that for the same stacked layers, though high stacking number favors writeability, it is limited to three layers due to source/drain series resistances. The double stacking is feasible for balanced read and write performances.