A VLSI architecture for intra prediction for a HEVC decoder

One of the key changes introduced in the High Efficiency Video Coding (HEVC) in comparison to the H.264/AVC is a revised algorithm of Intra prediction. Unfortunately, along with a significant improvement in the performance, its complexity has also been increased. This growth is particularly noticeable in the design of potential hardware architectures, due to a substantial augmentation in the number of supported modes and block sizes. This article presents an Intra prediction module architecture for the decoder, compliant with the Main profile of the sixth version of the HEVC draft. It allows the throughput of at least one sample per clock cycle at a moderate consumption of hardware resources, what should be enough to provide support for HDTV sequences in real-time for a 100 MHz clock.