Design and implementation of four bit arithmetic and logic unit using hybrid single electron transistor and MOSFET at 120nm technology

Author

Raut, Vaishali ; Dakhole, P.K.

Author_Institution

Electron. & Telecommun. Dept., G.H. Raisoni Coll. of Eng. & Manage., India

fYear

2015

fDate

8-10 Jan. 2015

Firstpage

1

Lastpage

6

Abstract

Low power design requires optimization at all levels and recent development in nanoscale devices unlock the idea of hybridization due to which power consumption of a system can be controlled. The implementation of hybrid techniques for the designing of four bit arithmetic and logic unit with low power dissipation is presented in these paper. The characteristics of SET as a low power device and MOSFET as a high speed device produces unique innovations, which is not possible to achieve with only CMOS circuit. The basic hybrid gates designed and simulated as well as new XOR gate is designed for reducing the power dissipation in implementation of four bit hybrid arithmetic and logic unit. Three different full adders designed, simulated and compared in terms of power dissipation.

Keywords

CMOS logic circuits; MOSFET; adders; integrated circuit design; logic design; logic gates; low-power electronics; single electron transistors; CMOS circuit; MOSFET; SET; XOR gate; adder; arithmetic unit; hybrid gate; hybrid single electron transistor; logic unit; low power design; low power dissipation; nanoscale device; optimization; power consumption; size 120 nm; word length 4 bit; Adders; CMOS integrated circuits; Hybrid power systems; Logic gates; Power dissipation; Single electron transistors; Transistors; CMOS; Coulomb blockade; Hybrid single-electron transistor; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Pervasive Computing (ICPC), 2015 International Conference on

Conference_Location

Pune

Type

conf

DOI

10.1109/PERVASIVE.2015.7087063

Filename

7087063