Comparison of DAC architectures of sar ADCS

A study of different Analog to Digital Converters (ADCs) based on Successive Approximation Register (SAR) architecture is presented. A double-tail latch type comparator is incorporated in all the designs due to its low power consumption and good speed. For the Digital to Analog Converter (DAC) unit, three different structures such as conventional binary weighed capacitor array, charge redistribution capacitor array, and capacitor splitting capacitor array are used. All the three different SAR ADCs are designed and simulated using 0.18 µm CMOS technology and their performance are compared.