Asynchronous timing model for high-level synthesis of DSP applications

In an asynchronous system, initiation and completion of operations are events that can occur at any instant and the operations have delays which are data dependent. Thus if an asynchronous timing model is considered, we can provide scheduling, resource-allocation strategy. Since one of the principal feature of the asynchronous systems is to exhibit average computation time, it will be interesting to use it as a timing model. In this paper we present a statistical approach to derive the average computation time of asynchronous components, first step toward High Level Synthesis. This method allows to reduce the critical path which in the case of a realtime application will be an excellent issue to reduce the number of operators.