The impact of data characteristics on hardware selection for low-power DSP

Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there is no analysis based on detailed simulation of multipliers available. This paper considers the power consumption of a number of multiplier structures such as array and Wallace Tree multipliers and examines how the power varies with data wordlengths and different applications (e.g. image and speech). In all cases results were obtained from EPIC PowerMill™ simulations of synthesised circuit layouts, a process which is accepted to be within 5% of the actual silicon. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems. The application of the findings to system level design can result in savings of up to 40.