Automatic generation of a VLSI parallel architecture for QRS detection

QRS is the dominant complex in the Electrocardiogram (ECG). Its accurate detection is of fundamental importance to reliable ECG interpretation and hence, to all systems analyzing the ECG signal (e.g. Heart-monitoring). Syntactic methods are a very powerful tool for QRS detection, since they can easily describe complex patterns, but their high computational cost prevents their implementation for real time applications. In this paper, we present a VLSI architecture for ECG signal processing, automatically derived using a nested loop parallelization method. This architecture detects the QRS complex by parsing the corresponding to the ECG signal input string, based on an attribute grammar describing it.