Title :
Efficient implementation of the row-column 8×8 IDCT on VLIW architectures
Author :
Sakellariou, Rizos ; Eisenbeis, Christine ; Knijnenburg, Peter
Author_Institution :
Dept. of Comput. Sci., Univ. of Manchester, Manchester, UK
Abstract :
This paper experiments with a methodology for mapping the 8×8 row-column Inverse Discrete Cosine Transform on general-purpose Very Long Instruction Word architectures. By exploiting the parallelism inherent in the algorithm, the results obtained indicate that such processors, using sufficiently advanced compilers, can provide satisfactory performance at low cost without need to resort to special-purpose hardware or time-consuming hand-tuning of codes.
Keywords :
discrete cosine transforms; microprocessor chips; parallel architectures; program compilers; VLIW architectures; advanced compilers; inverse discrete cosine transform; processors; row-column IDCT; special-purpose hardware; time-consuming hand-tuning code; very long instruction word architectures; Computer architecture; Discrete cosine transforms; Multimedia communication; Parallel processing; Program processors; Schedules; VLIW;
Conference_Titel :
Signal Processing Conference (EUSIPCO 1998), 9th European
Conference_Location :
Rhodes
Print_ISBN :
978-960-7620-06-4
