DocumentCode :
703572
Title :
DSP implementation and performance evaluation of a stereo echo canceler with pre-processing
Author :
Joncour, Yann ; Sugiyama, Akihiko ; Hirano, Akihiro
Author_Institution :
C&C Media Res. Labs., NEC Corp., Kawasaki, Japan
fYear :
1998
fDate :
8-11 Sept. 1998
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents implementation and performance evaluation of a stereo echo canceler with pre-processing. A two-tap time-varying filter located in one of the two channels periodically delays the input signal by one sample. By this pre-processing, the correct echo-path identification is achieved. This stereo echo canceler is implemented by four 32-bit floating-point digital signal processors (ADSP-21062). Experimental results show that the implemented echo canceler can reduce the echo by approximately 25 dB for a white Gaussian signal and by 23 dB on average for a speech signal. The ERLE is not degraded by talker movements in the remote room. The Mean Opinion Score for the implemented echo canceler is 0.55-point and 0.48-point higher than that for the echo canceler based on linear combination for round-trip delays of 100 ms and 600 ms, respectively.
Keywords :
echo suppression; speech processing; ADSP-21062; floating-point digital signal processors; linear combination; mean opinion score; performance evaluation; preprocessing; round-trip delays; speech signal; stereo echo canceler; time 100 ms; time 600 ms; white Gaussian signal; word length 32 bit; Codecs; Delays; Microcomputers; Speech;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Conference (EUSIPCO 1998), 9th European
Conference_Location :
Rhodes
Print_ISBN :
978-960-7620-06-4
Type :
conf
Filename :
7090043
Link To Document :
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