Title :
Minimizing the number of process corner simulations during design verification
Author :
Shoniker, Michael ; Cockburn, Bruce F. ; Jie Han ; Pedrycz, Witold
Author_Institution :
Univ. of Alberta, Edmonton, AB, Canada
Abstract :
Integrated circuit designs need to be verified in simulation over a large number of process corners that represent the expected range of transistor properties, supply voltages, and die temperatures. Each process corner can require substantial simulation time. Unfortunately, the required number of corners has been growing rapidly in the latest semiconductor technologies. We consider the problem of minimizing the required number of process corner simulations by iteratively learning a model of the output functions in order to confidently estimate key maximum and/or minimum properties of those functions. Depending on the output function, the required number of corner simulations can be reduced by factors of up to 95%.
Keywords :
circuit simulation; electronic design automation; integrated circuit design; transistor circuits; Integrated circuit designs; design verification; die temperatures; output functions; process corner simulations; semiconductor technologies; supply voltages; transistor properties; Automation; Decision support systems; Europe; Integrated circuit modeling; Semiconductor process modeling; Transistors; Uncertainty; Adaptive algorithms; Gaussian processes; circuit simulation; design automation; function approximation; robustness; unsupervised learning;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8