• DocumentCode
    703856
  • Title

    Using structural relations for checking combinationality of cyclic circuits

  • Author

    Wan-Chen Weng ; Yung-Chih Chen ; Jui-Hung Chen ; Ching-Yi Huang ; Chun-Yao Wang

  • Author_Institution
    Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2015
  • fDate
    9-13 March 2015
  • Firstpage
    325
  • Lastpage
    328
  • Abstract
    Functionality and combinationality are two main issues that have to be dealt with in cyclic combinational circuits, which are combinational circuits containing loops. Cyclic circuits are combinational if nodes within the circuits have definite values under all input assignments. For a cyclified circuit, we have to check whether it is combinational or not. Thus, this paper proposes an efficient two-stage algorithm to verify the combinationality of cyclic circuits. A set of cyclified IWLS 2005 benchmarks are performed to demonstrate the efficiency of the proposed algorithm. Compared to the state-of-the-art algorithm, our approach has a speedup of about 4000 times on average.
  • Keywords
    combinational circuits; logic design; cyclic combinational circuits; cyclified IWLS 2005 benchmarks; cyclified circuit; Algorithm design and analysis; Benchmark testing; Combinational circuits; Delays; Integrated circuit modeling; Logic gates; Open systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
  • Conference_Location
    Grenoble
  • Print_ISBN
    978-3-9815-3704-8
  • Type

    conf

  • Filename
    7092408