DocumentCode :
703914
Title :
A neural machine interface architecture for real-time artificial lower limb control
Author :
Kane, Jason ; Qing Yang ; Hernandez, Robert ; Simoneau, Willard ; Seaton, Matthew
Author_Institution :
Dept. of Electr., Comput., & Biomed. Eng., Univ. of Rhode Island, Kingston, RI, USA
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
633
Lastpage :
636
Abstract :
This paper presents a novel architecture of a lower limb neural machine interface (NMI) for determination of user intent. Our new design and implementation paves the way for future bionic legs that require high speed real-time deterministic response, high accuracy, easy portability, and low power consumption. A working FPGA-based prototype has been built, and experiments have shown that it achieves average performance gains of around 8x that of the equivalent software algorithm running on an Intel Core i7 2670QM, or 24x that of an Intel Atom Z530 with no perceivable loss in accuracy. Furthermore, our fully pipelined and parallel non-linear support vector machine-based FPGA implementation led to a 6.4x speedup over an equivalent GPU-based design. In this paper, we also characterize our achieved timing margin to show that our design is capable of supporting real-time wireless communications. With additional refinement, such a wireless personal area network (PAN) system will provide improved flexibility on an individual basis for electromyography (EMG) sensor placement.
Keywords :
artificial limbs; brain-computer interfaces; field programmable gate arrays; parallel processing; personal area networks; pipeline processing; support vector machines; PAN system; neural machine interface architecture; nonlinear support vector machine; parallel FPGA implementation; pipelined FPGA implementation; real-time artificial lower limb control; real-time wireless communications; timing margin; user intent determination; wireless personal area network; Electromyography; Feature extraction; Field programmable gate arrays; Hardware; Real-time systems; Support vector machines; Wireless communication; Artificial Leg Control; Field Programmable Gate Arrays (FPGA); Neural Machine Interface (NMI); Parallel Architectures; Support Vector Machines (SVM);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092466
Link To Document :
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