DocumentCode :
703977
Title :
DSP based programmable FHD HEVC decoder
Author :
Sangjo Lee ; Joonho Song ; Wonchang Lee ; Doohyun Kim ; Jaehyun Kim ; Shihwa Lee
Author_Institution :
DMC R&D Center, Samsung Electron., Suwon, South Korea
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
972
Lastpage :
973
Abstract :
A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV System on Chip (SoC) and is used for FHD High Efficiency Video Coding (HEVC) decoder under 400MHz. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.
Keywords :
coprocessors; decoding; digital television; multiprocessing systems; system-on-chip; video coding; High Efficiency Video Coding decoder; coprocessor system; digital TV SoC; digital TV system on chip; hardware design; multicore DSP based programmable FHD HEVC decoder; parallelize algorithm development; programmable video decoding system; software optimization; Computer architecture; Decoding; Hardware; Instruction sets; SDRAM; Standards; VLIW; DSP; FHD; HEVC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092529
Link To Document :
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